CuSha is a CUDA-based vertex-centric graph processing framework that uses G-Shards and Concatenated Windows (CW) representations to store graphs inside the GPU global memory. G-Shards and CW consume more space compared to Compressed Sparse Row (CSR) format but on the other hand provide better performance due to GPU-friendly representations. For completeness, provided package also includes Virtual Warp-Centric (VWC) processing method for GPU and a multi-threaded CPU implementation, both using CSR representation. CPU implementation utilizes Pthreads.
| Riverside Optimizing Compiler for Configurable Computing (ROCCC) 2.0:
An open source C-to-VHDL compiler infrastructure tool that builds upon the experience gained from the ROCCC toolset.
It is designed for the development of code accelerators that are mapped to FPGAs.
ROCCC 2.0 maintains all the extensive compiler optimizations developed in ROCCC
(e.g. data re-use through smart buffers, systolic array generation and general loop and procedure levels optimizations).
It introduces two novel features that simplify the design of hardware code accelerators: modular bottom-up designs and platform interface abstractions.
|NePSim is the first open-source integrated infrastructure for analyzing and optimizing NP design and power dissipation at architecture-level. NePSim contains a cycle-accurate simulator for a typical NP architecture, an automatic verification framework for testing and validation, and a power estimation model for measuring the power consumption of the simulated NP. NePSim achieves high accuracy in both performance and power modeling. ||NePSim|
|The eBlock simulator models many of the eBlock prototypes. Users can then build and test before ever having to use physical blocks. For advanced users we also have the option of a partitioning tool which simplifies eBlock systems into a system of smaller blocks accomplishing the equivalent functionality but utilizes programmable eBlocks. The partitioner automatically generates the corresponding code.
|PAC (Performance Assertion Checker) is an automatic checker generation tool for Logic of Constraints (LOC). It takes LOC formulas and generates corresponding C++ checkers, which can be used as static trace checkers or integrated into simulation tools as assertion monitors. In addition, LOC Trace Checker Generator (LOCGen) is developed to directly generate trace checkers with the same data structures and algorithms as used in PAC. It takes a standard LOC formula specification, an event and annotation specification, and a trace format specification, and generates a C++ program to analyze traces for LOC formulas.||PAC|